Adaptative packet/circuit switched transportation method and system

ABSTRACT

Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network. Each complex frame contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256) and concludes a succession of subframes delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Divison Multiplex Frames (125 microseconds) and n being an integer number equal to or greater than 1 which depends upon the medium link bit rate and e being a period of time lower than a medium link bit period. The subframes have a duration equal to or less than T, each subframe containing an integer number of bits Nsi, said integer number being allocated to carry an integer number of circuit switched bit slots and the remaining bits being dedicated to asynchronous packet switched bits. The R bits remaining in the complex frame, with ##EQU1## are used for flag bits f and r=R-f bits are used for asynchronous packet switched bits.

DESCRIPTION OF THE INVENTION

1. Field of the Invention

This invention relates to a method and a system for providing the packetswitching function along with the circuit switching function thru atelecommunication network.

2. Background Art

A telecommunication network is made of various nodes to which terminalsare attached through communication controllers and which are linkedthrough multiplex links.

Due to the bursty nature of most of the data to be transported, packetswitching networks have been implemented to optimize the utilization ofthe network resources. However packet transportation implies large andvariable transit delays that cannot be suffered by some real timeapplications. The variation of the transit delay can only be compensatedby means of additional buffers at the end users, which is costly andimplies delays.

On the other hand, circuit switch networks provide low constant transitdelays, but lead to a bad utilization of the network links when burstydata is to be transported through the network.

The ISDN network (Integrated Service Digital Network) described in "I"series of International Telegraph and Telephone Consulative Commitee(CCITT) Recommendations is the present approach to circuit switching andpacket switching integration. However the networks using the ISDNintegration technique are not optimized for the data packet trafficsince the bandwidth allocated to packet traffic is channelized.Furthermore the ISDN technique requires dedicated networks equipment,such as digital carriers.

Actually, most of the packet and circuit switching networks which intendto offer the ISDN services will use different packet and circuitequipments and for a long migration period and this will result in aduplication of the equipments and adapters. Reference is made to theIndustry ISDN Seminar, Mar. 11, 1985 by Bell Communication Research.

This type of networks which integrate the transportation of charactercoded data and non coded information NCI such as voice, do not optimizethe network resources (links, nodes etc.)

On one side, the users will need to transport a wide range ofinformation types for example, coded and non coded, compressed or noncompressed, real time or batch, voice or video, etc. On the other sidethe common carriers will offer a wide range of facilities with linksable to support high bit rate which can be higher than 2 Megabits persecond based on the current 64 Kilobits per second Time DivisionMultiplex TDM standard, coexisting with analog facilities, e.g. intercountry analog primary groups, therefore there is a need to buildnetwork nodes able to handle any type of information and to use allavailable transportation media of any type and of any speed.

SUMMARY OF THE INVENTION

In this environment an object of the present invention is to provide amethod and a system which optimize the bandwidth use on any type of linkwhile providing the transportation of any type of information in atelecommunication network.

Another object of the invention is to provide such a method and a systemwhich do not require a global synchronization of the network lines.

Another object of the invention is to provide such a method and a systemwhich insures a dynamic allocation of the bandwith to circuit or packettraffic according to the user activity on a per call basis.

The transportation system and method according to the invention is to beused in a telecommunication network for exchanging circuit switchedinformation which corresponds to a synchronous traffic, and packetswitched information which corresponds to an asynchronous traffic,between nodes connected through a medium link operating at any bit rate.

The method and system according to the present invention allow theconventional packet switching function along with the circuit switchingfunction to be provided thru the telecommunication network, sharing thesame links and nodes with the three following characteristics:

any type of link carriers can be used,

circuit subchannels are compatible with the worldwide telephonenetworks.

the bandwidth left by a non used circuit subchannel is automaticallyreused for packet traffic,

The method and system consists in configuring in each transmittingadapter of a network node, a succession of complex frames. Each complexframe contains an integer number of bits equal to Nc and is made of asucession of subframes. The complex frames are delimited by flags insuch a way that the period between two flags is equal to nT+e, T beingthe period of existing Time Division Multiplex frames which for thepresent time is equal to 125 microseconds, n is an integer number higheror equal to 1 which depends on the medium speed and e is lower than themedium link bit period.

The subframes have a duration less or equal to T and each subframecontains an integer number of bits Ns. The Ns bits are allocated to aninteger number of circuit switched bit slots and the remaining bits areused to carry asynchronous packet bits.

The R bits remaining in the complex frame, with R=Nc-nNsi are used tocarry f flag bits and r=R-f potential padding bits which are filled withasynchronous packet switched bits.

For a given value v of the medium link speed there is a set of values n,Ns and R which meets the above requirements. The specific values whichare chosen in each transmitting adapter depend upon constraints such asperformances or implementation of the adapter. In a preferred embodimentof the invention Ns is chosen as close as possible to the number of bitscontained in T to avoid the bit jitter in the complex frame.

The residual r bits may be placed at the end of the complex frames ormay be spread in the specified subframes. In the first case, thesubframes contain the fixed number Ns of bits and in the second case,they contain a variable number of bits so that a subframe i contains Nsibits. The residual number of bits R1 at the end of the complex frame isequal to ##EQU2## In that case, the flag is comprised in these R1 bitsand there are r1 residual packet bits.

This invention also relates to a mechanism for dynamically allocatingthe circuit slots of the complex frames according to the user activityon a per call basis.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows schematically a telecommunication network wherein thepresent invention may be implemented.

FIGS. 2-A and 2-B show the complex frames which are generated accordingto the method of the present invention.

FIG. 3 shows how the parameters of the complex frames are calculated.

FIG. 4 shows the paths for packet and circuit bits in two nodes of thenetworks.

FIG. 5 shows how packet bits from successive frames are assembled toconstitute a complete packet.

FIG. 6 shows the transmitting means for generating the complex frames onthe transmit interface of a outgoing medium link connected to a node.

FIG. 7 shows the receiving means receiving the complex frame from thereceive interface of an incoming link connected to a node.

FIG. 8 shows circuit 56 of the transmitting means.

FIG. 9 shows circuit 128-1 of the receiving means.

FIG. 10 shows two adjacent nodes in the network and shows schematicallythe protocols and interfaces defined in the system according to theinvention.

FIG. 11 shows the call set up flow which results in dynamicallyallocating a circuit slot in the complex frames.

DETAILED DESCRIPTION OF THE INVENTION

A telecommunication network, as schematically shown in FIG. 1 comprisesa plurality of nodes, four of which 1, 2, 3, 4 are represented. Aplurality of circuit switched type users C and a plurality of packetswitched type users P are attached to each node. The nodes are linkedthrough medium links, the links between different nodes may operate atany speed v higher than u.64 kilobits per second, u being the number ofcircuit switched users. The users connected to a node share the linkbandwidth in such a way that according to the present invention, at agiven instant the circuit switched users exchange the non charactercoded information (NCI), such as voice, in subchannels and the remainingbandwidth is used for packet traffic. This is schematically representedin FIG. 1 by the hatched part of the links.

The circuit type users operates at 64 kilobits per second, 8 kHzstructured which corresponds to the presently conventional bit rate,i.e. 8 bits every 125 microseconds. The man skilled in the art will beable to adapt the method according to the invention, if different bitrates become available in the future.

According to the present invention, the transmitting adapter of eachnode comprises means to cause the data and non coded information NCIbits such as voice emanating from the packet switched type users andfrom the circuit switched type users connected to the node to betransmitted on the medium link in complex frames having the structureshown in FIG. 2. The structure of the complex frames is determined usingthe method of the present invention which comprises the stepsillustrated in FIG. 3.

For the sake of the explanation of the invention, the structure of thetheoreatical complex frame is shown in FIG. 2-A. FIG. 2-B shows thecomplex frame which is generated by the means described in FIG. 6 to besent on the medium link.

The complex frame contains Nc or Nc+1 bits and has a duration equal tonT+e, T being the conventional time division multiplex slot which forthe present time is equal to 125 microseconds, n being an integer equalor higher than 1 and e being lower than a medium link bit period, ndepends upon the link speed and is calculated as will be described inreference to FIG. 3.

The complex frames contain n subframes, each subframe has a durationequal or less than T so as to contain an integer number Ns of bits. TheNs bits of a subframe are allocated to the transportation of a variablenumber of circuit switched bit slots. The number of slots depends uponthe user need, two slots are represented in FIG. 2, and the remainingbits are allocated to the transport of packet switched bits.

As above described, in the preferred embodiment of the presentinvention, the circuit user bit slots are dynamically allocated toactive circuit users, so that the subframe structure changes dependingupon the circuit user activity and the number of packet data bitsvaries. However, in specific applications this number may be fixed andthe slots may be permanently allocated whether they are used or not.

The complex frames are delimited through a f-bit flag which is part ofthe R bits remaining at the end of the complex frame with R=Nc-nNs.

In cases where R is higher than f, the r=R-f bits are filled withasynchronous traffic bits. The residual r bits, may be spread in givensubframes to avoid jitter. This causes a variable determined number ofbits Nsi to be contained in the subframes. This result in a differentnumber R1 of residual bits at the end of the complex frame which isequal to ##EQU3##

As shown in FIG. 2-B, the flag is generated at the next medium linkclock time following the nT boundaries. Then the n subframes comprisingNs bits and the r residual bits are sent on the medium link.

The invention will be more specifically described assuming that thesubframes contain a constant number of bits, and the man skilled in theart can easily adapt the means which will be described later on toprovide subframes having a variable number of bits according to theabove requirements.

As can be seen in the hereafter table, depending upon the link speedversus 64 kbps, the complex frames do not contain a constant number ofbits, however the variation of the bit number Nc in consecutive complexframes is only equal to 1. Thus, the complex frame limit is known by thereceiving end thanks to the flag detection and bit counting. The minimumflag length which allows the complex frame delimitation is equal to 2bits, however since the flag may also be used for other purposes a 8 bitflag is used in most applications. The only requirement is that the flagbegins by 01 or 10. When the lowest possible number Nc of bits a complexframe have been counted from the beginning of the opening flag, the twonext bits are analyzed. An equality of these bits with the two firstbits of the flags, means that the frame contains Nc bits, if not, theframe contains Nc+1 bits. This is illustrated below:

Flag 01

. XXXXX represent the frame bits which can be equal to 0 or 1 ##STR1##

Consequently, when Nc bits have been counted from the beginning of thepreceding flag, the two next bits including the first bit of the flagand the additional bit of the frame, if any, cannot simulate the 01delimiting pattern whatever the value of this additional frame bit canbe. When Nc bits have been counted, the detection of the 01 patternindicates that the frame contains Nc bits.

A flag beginning with 10 has also the same property.

The method which is used for configuring the complex frames at eachtransmitting ends is represented in FIG. 3.

The speed of the medium link and the desired approximate number of bitsNa in the complex frames determine the complex frame structure. In aspecific embodiment of the invention, which for the present time isintended to be used with medium link speed lower or equal to 2.048megabits per second, Na is chosen equal to 256 so that the number Nc beas close as possible to 256 bits, in order to keep a flag overhead ratiof/Nc in the same range as the one used for classical TDM first ordermultiplex links.

The method consists in calculating the link bit time t which is equal to1/v, where v is the bit rate on the medium link. (Step 1)

Then the number of bits in the time division multiplex slot T iscalculated. The number of bits Ns in each subframe is equal to theinteger part of this number. Assuming that v is expressed in kilobitsper second and T is equal to 125 microseconds, Ns is the integer part ofthe product 125.v.10⁻³. (Step 2)

Then the number n of subframes is calculated, this number is the integerpart of the quotient Na/Ns. In the specific embodiment described in FIG.3, it is the integer part of 256/Ns. (Step 3)

Then the residual number R of bits is calculated (Step 4). This numberis equal the difference between the real number of bits comprised in Tand Ns, multiplied by the subframe number n and can be expressed asfollows:

n.(T.v.10⁻³ -Ns)

This number R is compared to f, (Step 5). If it is higher or equal to f,the number of bits in the subframes is made equal to the value of Nscalculated in step 2. If not the number of bits in the subframes is madeequal to Ns calculated in step 2 minus 1. The residual number R of bitscorresponding to this new subframe number is calculated.

Steps 4 and 5 are resumed as long as the residual number R is not higheror equal to f.

This method also applies when it is desired to have the residual bitsspread in the subframes. In that case the theoretical numbers Ns and Rare calculated according to the above described method and the residualbits are placed in specific identified subframes and the new residualbit number R1 is calculated so that the r1 bits, with r1=R1-f, if anyremaining at the end of the complex frames may be filled withasynchronous traffic bits.

The following table gives the various values which are obtainedaccording to the above method for four medium link speeds.

                  TABLE 1                                                         ______________________________________                                        Medi-         Maximum                                                         um    Ns bits number of Number           Number of                            link  per     circuit   n of             bits Nc or                           speed sub-    users at  sub-             Nc + 1 in                            V kbps                                                                              frame   64 kbps   frames r     f   complex                              ______________________________________                                         72    8      1         28     20    8   252                                  132   15      1         16     16    8   264                                  230   27      3          9     7 or 8                                                                              8   258 or 259                           1544  185     23         1      0    8   193                                  ______________________________________                                    

FIG. 4 shows two nodes of the telecommunication network. Each nodecomprises similar means, they are referenced by the same number with asuffix 1 for the means in node 1 and 2 for means in node 2. Each nodecomprises medium link adapters 10 and 11 made of receiver/transmittermeans and including the specific means which are needed to implement themethod according to the invention. The adapters are connected to mediumlinks, each link having a specific speed, so that the complex frames onthe different links have different configurations. These frames arebuilt in the transmitter means of the adapters to be sent on the links.The parameters n, Ns, r of the complex frames are made known to thecorresponding receiver means, in order the received bits may beprocessed. The complex frames are shown in a schematic way on thedifferent links.

Two paths are provided in each node. One path CP is dedicated to thecircuit switched bits (synchronous path) which have to be transmittedwith constant and very short delay (<500 microseconds) and the otherpath PP is dedicated to the packet switched bits (asynchronous path)which are bufferized and processed in packet handling means 14.

FIG. 5 shows how packets ready to be switched could be reconstructed inthe receiving node from the asynchronous flow made of packet bits.

The consecutive received complex frames contain circuit user slots C1and C2 for example, assuming that two circuit users are involved in acall and packet switcked bits P. Complex frame (m-1) contains packetbits P0, complex frame m contains packet bits P1, P2, P3, P4 and complexframe m+1 contains packet bits P5. For the purpose of illustration, itis assumed that a packet ready to be switched: i.e. constituted of apacket header containing the information which is necessary to route andswitch the packet and packet data, comprising packet bits P1, P2, P3, P4from complex frame m and parts of packet bits P0 and P5.

FIGS. 6 and 7 show the specific means which are needed in the mediumlink adapters to implement the method according to the invention.

FIG. 6 represents the transmitting means and FIG. 7 represents thereceiving means. For the sake of explanation, it is assumed that FIG. 6shows the transmitting means of a first transmitting node and FIG. 7shows the receiving means of a second receiving node. It is to beunderstood that, each adapter comprises receiving and transmitting meanssuch as shown in FIGS. 6 and 7. The medium access manager and the finitestate machine are common to the receiving and transmitting means in anadapter.

In the preferred embodiment of the transmitting means, the medium linkaccess manager 20 computes the link parameters according to the methodof FIG. 3 or by consulting tables which are built according to themethod of FIG. 3.

In other embodiment of the invention, the parameters can be provided tothe manager by external means, such as operator intervention.

The medium access manager also provides event indications to finitestate machine 32, EMG1, 2, 3, and receives signal SMG3 from finite statemachine 32 as will be described later on in connection with the finitestate machine diagram.

The medium link access manager 20 provides through output bus 21 thelink parameters Ns, n and the slot allocation to registers 22 and 24 andto slot table 26, respectively. Thus the slot table 26 contains anindication of the slots of the subframes which are allocated to circuitusers. At each subframe generation, the slot table is read and itsoutput 28 is used in logic circuit 30 to generate Packet or Circuit, Por C ENABLE signals.

The medium access protocol is managed through finite state machine 32which is a logic providing control signals when specific events occur.The operation of this machine will be detailed later. It is connected tothree lines 33, 34 and 35 from the associated receiving means, saidlines carrying the RECEIVED IDLE PATTERN, RECEIVE SYNCHRO REQUEST andthe RECEIVE LOST SYNCHRO signals respectively and to output bus 21.Depending upon the received events it generates on its output lines 38,39, 40, 41 control signals DISABLED, SEND SYNCHRO PATTERN, SEND SYNCHROREQUEST and OPERATION respectively.

Bit counter 44 working under control of a clock 48 operating at themedium speed counts the bits and the subframes. Counter 46 counts thesubframes. The contents of counters 44 and 46 are compared with the Nsand n registers 22 and 24 by comparators 47 and 49. The output 50 ofcomparator 47 is provided to subframe counter 46 so as to cause thiscounter to be incremented each time an equality is detected bycomparator 47.

Outputs 50 and 51 of the comparators, output 28 of slot table 26 areprovided to logic 30 to generate the P ENABLE, C ENABLE and FLAG ENABLEsignals at the correct times to build the complex frame according to themethod of the present invention.

Logic 30 also receives the OPERATION control signal from finite statemachine 32.

Flag and r sending logic control circuit 56 working under control ofT-pulse counter 57, medium link bit clock 48 and outputs 50 and 51 ofcomparators 47 and 49 allows specific patterns to be sent on the mediumlink at given instants under control of the signals on output lines 39,40 and 41 of finite state machine 32. It also provides a reset countersignal on its output line 58. Output line 58 and output lines 50 and 51of comparators 47 and 49 are provided to OR circuits 52 and 54 whichprovide the reset signal to bit and subframe counters 44 and 46respectively.

Circuit 56 also generates on output line 60, a r sending control signalwhich is provided to logic 30 so as to cause the r residual packet bitsto be sent on the medium link in order to generate the complex frames asdescribed in reference to FIG. 2-B.

The different flags are generated by circuit 56 on output lines 62, 64and 66. As will be described later on, different flags have to be sentat given times. In a specific embodiment of the invention, 01111110 isthe normal complex frames delimiter, abort flag 01111111 is used torequest the synchronization and UCC flag is used for indicating to thereceiving means that a circuit user is added or deleted, in case thedynamic bandwidth allocation feature is implemented. If not, there is noneed of this UCC flag.

Consequently, generator 56 generates the medium flag 01111110 undercontrol of OPERATION and SEND SYNCHRO PATTERN signals on lines 41 and 39from finite state machine 32.

Circuit 56 generates the specific flag 01111111 under control of SENDSYNCHRO REQUEST line 40 from finite state machine 32.

In the preferred embodiment of the invention, circuit 56 generates theUSER CIRCUIT CHANGE pattern UCC which is used for changing the userslots in the subframes. This pattern is changed under control of themedium access manager 20, so that circuit 56 receives the pattern to begenerated on bus 21. This part has only to be provided when it isdesired to have the capability of adding or deleting circuit users. Whenthe circuit slots are permently allocated, this part is not required asall means which are required in connection with this capability.

The flag outputs 62, 64 and 66 of circuit 56 are provided to OR circuit72.

Circuit 56 also generates a flag sending control signal on line 68 whichis provided to logic 30 and which is also used during the initializationperiod to prevent the idle 111 . . . 11 configuration from being sent onthe medium link during the flag sending period as will be detailed lateron.

Circuit 56 generates a next slot signal on line 70, which is provided tothe slot table to cause the table to be scanned in order to have the Por C indication to be provided to logic 30 through output line 28 ofslot table 26.

The packet user bits from path PP and the circuit user bits from path CPor the specific patterns from the output of OR circuit 72 aretransmitted on medium link 96 at specific instant to build the complexframes through AND gates 74, 76 and 78 and OR gate 80. AND gate 74receives the P ENABLE signal from output line 84 of logic circuit 30 andthe packet switched bits from PP path. AND gate 76 receives the C ENABLEsignal from output line 86 of circuit 30 and the circuit switched bitsfrom path CP. AND gate 78 receive the FLAG ENABLE signal from outputline 88 of circuit 30 and the specific flag patterns from output of ORcircuit 72.

The outputs of AND gates 74, 76 and 78 are provided to OR circuit 80.The output of OR circuit 80 is provided to AND gate 81 which isconditioned when the medium link clock signal is positive, for example.The output of AND gate 81 set latch 83 which is reset when the mediumlink clock signal is negative. Thus latch 83 provides on its output thebit to be transmitted on the medium link 96.

OR circuit 82 receiving the DISABLED signal from output line 38 offinite state machine 32 has its output connected to OR circuit 80, sothat the idle configuration 11 . . . 1111 is sent on the medium link 96through AND gate 81 and latch 83 when the DISABLED signal is active.

AND gate 94 receiving the OPERATION signal from line 41 inverted byinverter 92 and the flag sending control signal from line 68 of circuit56, has its output connected to OR circuit 82 to send the all mark 111 .. . 111 configuration on medium link 96 during the initializationperiod, between flags.

An embodiment of circuit 56 will be described in reference to FIG. 8.

The receiving means shown in FIG. 7 will now be described, so that theoperation of the transmitting means will be explained in connection withthe operation of the receiving means.

In the receiving means which is assumed to be in the adapter of thesecond node to be linked to the first node comprising the transmittingmeans described in reference to FIG. 6, the adapter medium accessmanager 100 is represented.

The finite state machine 101 of the adapter is also schematically shownin FIG. 7, only OPERATION output line 103 which is needed for thereceiving operation is represented.

The link parameters Nc, n and Ns have to be known from the receivingmeans. They may be transmitted from the transmitting means or may becalculated in the receiving means. In a specific embodiment of theinvention, they are found in the receiving means by consulting tablescontaining the correlation between Nc and the desired parameters values,Nc being the number of bits received between two flags during theinitialization period, i.e. being an indication of the link speed.

The medium link parameters are loaded in Ns-register 102, n-register 104and slot table 106 through output bus 101.

The receiving means also comprises a bit counter 108 and a subframecounter 110. Bit counter 108 works under control of medium link clock112. Comparator 114 compares the content of counter 108 and Ns-register102 and comparator 116 compares the content of counter 110 andn-register 104 so as to generate signals on their output lines 115 and117 which are active when an equality is detected. Output lines 115 and117 are connected together with the output line 119 of slot table 106 tologic circuit 118. Logic circuit 118 generates P ENABLE or C ENABLEsignal on output lines 120 and 122 respectively.

The detection of an equality by comparators 114 and 116 causes counters108 and 110 to be reset.

The received bits on medium link 96 are provided to two AND gates 124and 126 by means of 8-bit shift register 127. AND gates 124 and 126 areconditioned by the P ENABLE and the C ENABLE signals on lines 120 and122 respectively. Their outputs are provided to the packet switched bithandling facility of the receiver and to the circuit switched bithandling facility, where the packet and circuit switched bits areprocessed in the conventional way. These facilities are not describedsince they are not the subject of the invention.

The received bits are also provided to circuit 128. Circuit 128comprises means 128-1 for detecting the flags and counting the bits inthe complex frames. In normal mode of operation, i.e. after theinitialization period, "r Received" output line 130 of circuit 128 isactivated so as to cause the P ENABLE signal at output of logic 118 tobe activated so that the r residual bits are provided to the packetswitched bit handling facility through AND gate 124.

It also detects the UCC flags which are transmitted to the slot tablethrough bus 132 in order the receiving means take into account thecircuit user change transmitted by the transmitting means and generatesthe RCV UCC signal on line 136 and the next slot signal on line 137which causes the content of slot table 106 to be scanned to cause the Pand C ENABLE signals to be activated according to the subframeconfigurations.

Circuit 128-1 generates a reset CTR signal on line 138 which is providedto OR circuits 140 and 142. The outputs of comparators 114 and 116 arealso provided to OR circuits 140 and 142 whose outputs control theresetting of counters 108 and 110.

The function of shift register 127 is to delay the received bits in sucha way that the flag detection may be performed in circuit 128.

Circuit 128 detects the flags in the received bits and from this flagdetection and the counting of bits, part 128-2 detects when thesynchronization is lost to generate the RCV LOST SYNCHRO and RCV SYNCHROREQUEST on lines 35 and 34. It also detects the all mark 11 . . . 111received bit stream to generate the RCV IDLE signal on line 33. Thesethree signals are sent to the transmitting means as shown in FIG. 6.

A specific embodiment of part 128-1 will be described in reference toFIG. 9.

The operation of the transmitting and receiving means will now bedescribed. Through the framing of the medium complex frame, the adjacentmedium access elements are able to exchange status information andsignals.

The different states are the following:

DISABLED: send idle pattern, i.e. 11 . . . 1111

ENABLED: send SYNCHRO (01111110) or SYNCHRO REQUEST (01111111) attransmitting end and SEARCH FOR RECEIVE SYNHRO at receiving end,

SYNCHRONIZED: receive SYNCHRO without SYNCHRO REQUEST and send SYNCHROwithout SYNCHRO REQUEST

OPERATIONAL: send/receive normal frame; send/receive User Circuit ChangeUCC

The finite state machine generates signals which depend upon theoccurrence of events. There are two kinds of signals and events, namelythe medium access manager events and signals and the medium link eventsand signals.

MANAGER EVENTS AND SIGNALS EVENTS:

EMG1: Load transmit medium access parameters Ns, n

EMG2: Load receive medium access parameters

EMG3: Add circuit user

SIGNALS

SMG1: User Circuit Change UCC

MEDIUM EVENTS AND SIGNALS EVENTS

EMD1: Receive idle, i.e. all mark

EMD2: Receive SYNCHRO REQUEST, i.e. 01111111 in place of flag

EMD3: Receive LOST SYNCHRO if not 01XXXXXX every medium frame

EMD4: Receive UCC, i.e. 010CXXXX in place of flags where 01 are the twodelimiting bits of the flags and the following zero indicates a circuituser change, C=0 means delete and C=1 means add and XXXX means the usernumber from 0000 to 1111. If there are more than 16 circuit users, theuser number to be added or deleted is encoded in two consecutive frames.In that case, in the first coding frame UCC value 010C1111 indicatesthat the circuit user number is encoded on two consecutive frames, saidnumber being equal to 1110 plus the value in the opening flag of thefollowing frame.

EMD5: receive normal frame

EMD6: receive SYNCHRO PATTERN: normal flag 01111110 with ones betweenthe flags, the medium frame is thus constituted of all ones.

SIGNALS

SMD1: Send idle

SMD2: Send SYNCHRO REQUEST

SMD3: Send SYNCHRO PATTERN

SMD4: Send normal frame

SMD5: Send circuit user change

The medium access protocol is managed according to the following statediagram through the finite state machine. ##STR2##

The operation of the transmitting means and receiving means located atboth ends of a medium link between two nodes 1 and 2 will now bedescribed.

Before an exchange is established between the two nodes, aninitialization period is required for synchronization purposes. Thisinitialization period encompasses the states DISABLED, ENABLED andSYNCHRONIZED as described in the state diagram.

From the node power on reset, the following operations are performed:

The idle configuration corresponding to all marks i.e. 11 . . . 111 issent by the transmitting means in node 1 and transmitting means in node2 which are in the disabled state. In that state the disabled signal isactive and OR gate 82 provides the idle pattern to the medium link 96.

The medium access manager in node 1 adapter loads the medium linkparameters in n and Ns registers 24 and 22 of transmitting means.

Then, the transmitting means generates through flag and r sendingcontrol circuit 56:

1-synchro pattern without synchro request if synchro not lost (SMD3)i.e.: ##STR3##

2-synchro pattern with synchro request if synchro lost, (SMD2) i.e.##STR4##

During this initialization period, P ENABLE signal is active so that allthe bits between the flags are handled as packet switched bits. Thenumber of bits between flags is an indication of the link speed which isused in the receiving means to get the Nc receiving parameter.

The 1 at the end of the flags indicate that synchro is requested at thereceiving end.

When the node 1 transmitting means detects that the SYNCHRO REQUEST line34 is no more active which means that synchro is no longer requested byreceiving means in node 2, the transmitting means in node 1 stop thesynchro pattern generation, and may switch from continuous flag sendingat n.T boundaries (SMD3) to normal or UCC flag sending: (SMD4 and SMD5).This corresponds to the OPERATIONAL state as defined in the statediagram.

The UCC flags which are thus transmitted are used in the receiving meansfor loading slot table 106.

If no UCC change is received from medium access manager the normal flagis sent instead of the UCC flag.

The link parameters computed by consulting tables containing theparameters as a function of Nc, are loaded in registers 102 and 104 ofreceiving means in node 2.

While in operational state, all mark bits are sent in the frame betweenthe flags by nodes 1 and 2, till one of the nodes has something totransmit. At that time, the slot table 26 in the transmitting means ofthe node having something to transmit is loaded according to the activecircuit user configuration.

In the receiving means, the slot table 106 is loaded through the UCCdetection in circuit 128.

Then, the complex normal frames built according to the method of theinvention are exchanged between the two nodes. Comparators 47 and 49detect the end of the subframes and of the n subframes in the complexframes. This detection and the scanning of the slot table causes P, Cand F ENABLE signal to be activated through gating logic 30 to build thecomplex frames as shown in FIG. 2-B.

In reference to FIGS. 8, 9 and 2-B, it will now be described how theflags and the r residual bits are generated and received.

In circuit 56, counter 57 counts the T (125 microseconds) periods, theT-pulse count at the output of counter 57 is compared with the n valueprovided by register 24 by comparator 200. Comparator 200 provides anactive signal when an equality is detected, this active signalindicating a nT boundary. When a nT boundary is detected, latch 202 isset. The output of latch 202 and the output of medium link clock 48 areprovided to AND gate 204.

The output of gate 204 sets FLAG latch 206 which thus provides on itsoutput 68 the FLAG SENDING control signal which is active at the bitclock time following a nT boundary. Latches 202 and 206 are reset by thesignal on line 208 at the output of comparator 210.

Comparator 210 compares the content of flag or slot bit counter 212which counts modulo eight, the medium bit clock from 48, with eight.This counter is reset at the medium link clock pulse following a nTboundary or at the eight-modulo bit boundary through OR gate 214 byconnecting output of comparator 210 to one OR gate 214 input. The otherinput of OR gate 214 is connected to the output of AND gate 204 and tothe output of comparator 210, so as to provide the reset signal on itsoutput 216.

Output 208 of comparator 210 is connected to the reset input of latches202 and 206 in order to reset the latches on the eight-bit boundaries soas to provide on output 68 of latch 206 a FLAG SENDING control signalwhich is active during the eight-bit flag periods.

Comparator output line 208 and FLAG SENDING control line 68 are providedto AND gate 218 which thus provides the reset signal for Ns and ncounters 22 and 24 (FIG. 6), on line 58. This signal is active at theend of the flag sending period, so that counters 22 and 24 are reset tozero in order to initiate the bit and subframe counting from that time.

The FLAG SENDING signal on line 68 is provided to frame counter 220which is a one-bit counter providing an indication that the sent framenumber is even or odd. This indication is required for sending normalflag or UCC flag alternatively.

Latch 224 is set at the n subframes boundary which is detected whencomparator 49 detects an equality and provides an active signal on line51 and is reset when the flag sending period begins which is detected bycomparator 200. Thus the output of comparator 200 is provided to thereset input of latch 224, which is thus set during the r sending periodand provides the r sending control signal on output 60, see FIG. 2-B forr sending period.

AND gate 226 is connected to the output 208 of comparator 210, to FLAGSENDING PERIOD line 68 through inverter 228 and to the output 60 oflatch 224 through inverter 230. Thus AND gate provides an active outputsignal on its output 70 at the eight-bit boundaries when FLAG SENDINGand r SENDING control signals are inactive. Thus AND gate 226 provideson line 70 the NEXT SLOT control signal which is used for scanning slottable 26.

The flag patterns 01111110 and 01111111 are contained in shift registers228 and 230 and the UCC flags are loaded in shift register 232 from bus21. The two most right bits of shift register 232 are set to 10 and theother bits indicates either the user change, if any, or are set to011111 if no user change is requested.

The shifting of registers 228, 230 and 232 is performed under control ofa logic circuit comprising AND gates 234, 236 and 238. These AND gatesare conditioned by the FLAG SENDING signal on line 8 and by the mediumbit clock signals from 48.

AND gate 234 provides an active shifting output signal when its thirdinput 240 is activated by means of OR gate 242 and AND gate 246. ANDgate 246 provides an active signal to one input of OR gate 240 when theOPERATION line 41 from finite state machine 32 is activated and when theoutput of frame counter 220 is at a first value corresponding to an oddframe number, for example. The second input of OR gate receives the SENDSYNCHRO PATTERN signal from output line 39 of finite state machine 32.

When these conditions are met, the normal 01111110 flag in register 228is provided on line 62 to be sent by AND gate 78 (FIG. 6) on medium link96.

AND gate 236 provides an active shifting output signal during the flagsending period when the SEND SYNCHRO REQUEST signal on line 40 fromfinite state machine 32 is activated. Thus during this period the abortflag 01111111 is provided to AND gate 78 (FIG. 6) to be sent on mediumlink 96.

AND gate 238 provides an active shifting output signal during the flagsending period when AND gate 248 is activated i.e. when the OPERATIONsignal on line 41 from finite state machine 32 is active and when framecounter 220 indicates an even frame number. Thus during this period, theUCC flag is provided to AND gate 78 to be sent on medium link 96.

FIG. 9 represents part 128-1 which performs the flag handling andgenerates the control signal which allows the P-ENABLE line 120 to beactivated when the r residual bits are received.

It comprises circuit 300 which detects the flag configuration during theinitialization period i.e. when the OPERATION signal 103 from finitestate machine 101 is not activated. Circuit 300 comprises one-counter302 which counts the ones in the received bit stream. Received bitstream from link 96 is provided to AND gate 310 which also receives themedium link clock signal from 112. The output of AND gate 310 isprovided to the one counter 302. Counter 302 content is compared withsix in comparator 304 so that when six consecutive ones are found in thereceived bit stream output 306 of comparator is activated and counter302 is reset.

The output 306 of comparator 304 is provided to AND gate 312 which alsoreceived the bit stream on link 96 inverted in inverter 314 and theOPERATION signal from line 103 inverted in inverter 316. Thus AND gate312 provides on its output line 318 a eight-bit flag detect signal whichis activated during the initialization period when six consecutive onesfollowed by a zero are received.

The value Nc or Nc+1 of the complex frame bits is found during theinitialization period by means of medium bit counter 320, Nc/Nc+1register 322, comparator 324 and AND gates 326. Counter 320 counts themedium link clock pulses from 112 and is reset by Ns and n counter resetsignal from line 138. The content of counter 320 is gated by AND gate326 when signal on line 318 is activated, in register 322. Consequentlyregister 322 contains the number of complex frame bits between twoflags.

The medium access manager loads the parameters calculated from Nc/Nc+and then becomes operational.

Then, register 322 content is compared with medium bit counter contentin comparator 324, which provides an output signal on line 328 which isactivated when medium bits counter 320 reaches the value recorded inregister 322. This active signal set latch 330 which controls thedetection of the 01 first bits of the received flag.

The output line 332 of latch 330 is provided to AND gate 334 to which isalso provided the received medium bit from link 96 and the last receivedmedium bit taken in register 127 (FIG. 7) and inverted in inverter 336.Consequently AND gate 334 provides an output signal on line 338indicating that the 01 delimiting configuration of the flag has beenreceived. This signal is used to preset at 2, slot bit counter 340. Slotbit counter counts the slot bits and its content is compared to 8 incomparator 342. Output line 344 of comparator 342 is activated when anequality is detected which indicates a 8-bit medium link boundary.Counter 340 is reset by the output of OR gate 346 which receives the8-bit flag detect signal on line 318 and the 8-bit medium link boundarysignal on line 344.

Latch 348 is set by the 2-bit defimiting pattern of the flag receivedsignal on line 338 and reset by the 8-bit medium link boundary signal online 344, so that it remains set during six bit period after thedetection of the 01 delimiting pattern of the flag.

The output line 350 of latch 348 is provided to AND gate 352 which alsoreceives the output line 344 of comparator 342. Thus the output signalof AND gate 352 is activated so as to provide the n and Ns counter resetsignal on line 138 during the flag detection period.

Latch 354 is set by the signal on line 138 and is reset by the 8-bitmedium link boundary signal 344 and provides to logic 118 in FIG. 7 theFLAG/UCC period signal on line 134 which is activated during eight bitperiod following the last bit of the flag. This signal is needed tocompensate the delay of the received bit stream introduced by shiftregister 127 in FIG. 7.

During the six bit period following the 01 delimiting configuration ofthe flag, the received medium bits are shifted in register 356 throughAND gate 358 the inputs of which are connected to link 96 and to outputline 350 of latch 348. Output bus 132 of UCC register 356 is provided tomedium access manager 100 and used to update slot table 106.

Output 350 of latch 348 provides the receive UCC signal on line 136which is provided to logic 118 of FIG. 7 corresponding to the event EMD4of finite state machine diagram.

AND gate 360 receives the 8-bit medium link boundary signal on line 344,the flag detection period signal on line 350 inverted by inverter 362and the r received signal on line 130 inverted in inverter 366 andprovides on its output line 137 the NEXT SLOT signal used for scanningslot table 106 in FIG. 7.

The r received signal on line 364 is provided by latch 368 which is setwhen comparator 117 detects an equality and is reset by the reset signalon line 138. Consequently this latch is set so as to activate the PENABLE line 120 for gating the r residual bits to the packet path PP.

It will now be described how the bandwidth is allocated as a function ofthe circuit user activity.

During the initialization phase, once the transmitting and receivingends are set into the operational state, i.e. once the parameters areloaded into the transmitting and receiving parameter registers, all bitswhich are transmitted between two flags are interpreted as packetswitched bits until circuit user slots are established. These bits arecoded and decoded by the ends as a normal HDLC channel. They constitutean HDLC string having a conventional format. Each HDLC frame contains apacket and the two first bytes of the data field of the packet contain alogical channel number LCN as defined in the CCITT recommendation X.25.This LCN value is set at 0 to indicate that the corresponding packet isa control packet used for managing a call in the network. Thisconstitutes a logical control channel similar to the "D" channel ofISDN. The packets having their LCN values different from 0 are used forother flow including the data flow.

The packet types are those defined by the X25 protocol, for example

Call request

Call connected

Clear request

Clear confirmation.

FIG. 10 represents two adjacent nodes in a network, one medium linkcomprising transmit and receive legs is represented between the twonodes. However, other medium links connecting said nodes with othernodes in the network are in fact provided as shematically shown inFIG. 1. FIG. 10 shows more specifically the protocols and interfacesdefined in the system according to the invention. Medium interface 400defines the medium complex frames. Medium access interface 402 definesthe commands used by the medium access manager to control the mediumaccess elements such as shown in FIGS. 6 and 7, to add or releasecircuit switch bandwidth by direct action on the complex frame.

Medium configuration control MCC interface 404 defines the format of themessages i.e. packet bits circulating on logical channel 0 (LCN=0) thatare the control packets as explained above.

Circuit switched function interface 406 defines the commands to thecircuit switching function 408 in order to synchronize this functionwith the medium configuration. For this purpose, circuit switch function408 comprises two switching tables 409. These tables are updated byservice manager 412 through interface 406 so as to correlate the complexframe slot number on the receive leg of an input link of the node to thecomplex frame slot number on the transmit leg of the output link whichis used for routing the call packets. In the end nodes i.e. originatorand destination nodes, the switching tables correlate the circuit usernumber with one link and incoming and outgoing slots on this link.

Packet switched function interface 410 defines the necessary commandsand signals between the service manager 412 and the packet switchedfunction 414 in order to manage the packet flow including the data andcontrol packet flows.

Network service interface 416 defines the messages exchanged between thesystem manager 418 and the network service function which includes theconfiguration service, the directory service, the measurement serviceand the maintenance service.

There are two kinds of protocols, namely the medium access protocol MAPthat describes the exchanges over the medium at medium complex framelevel and which has been described in connection with FIGS. 6 and 7 andthe service manager protocol SMP that describes the exchanges betweentwo system managers.

The residual clear channel is configured inside the complex frames builtas described above, to carry bit packets using the virtualcircuit/logical channel number VC/LCN of the X25 protocol for example.

As already explained, the LCN=0 is reserved and the packet circulatingon this LCN are routed to the system service manager 418, as a networkservice communication channel used in cooperation with the metworkconfiguration services. This channel is schematically shown as theconfiguration service channel CSC in FIG. 10.

FIG. 11 shows the call set up flow through a system node in a specificcase. It is assumed that circuit user X connected to originator node Awants to establish a call with circuit user Z connected to destinatornode C, through intermediate node B. Service manager 412 in node Acauses the call initiation phase to be entered. During this phase usingthe asynchronous packet flow (LCN=0), a call request packet is sent bythe originator node A to node B. This packet includes the called numberand potentially the calling number, information indicating that acircuit switched call is to be established and the slot number assignedto user X on the incoming leg of link L1 connecting node A to node B.The opening flag of the subsequent complex frame generated by thetransmitting means in node A is set to a value 0101"xx", indicating thata circuit user is to be added and that slot number "xx" is assigned toit. For example if the complex frames contained 2 circuit slots, slot 3is assigned to user X in the subsequent transmitted complex frames. Theslot table of the transmitting means in node A is updated. The decodingby node B of this new UCC flag indicates to node B, the complex framefrom which the change is effective.

Node B service manager waits for the two correlated information: callrequest packet and UCC flag 0101"xx" to determine whether it is thedestination node or whether the call request packet has to be propagatedto another node found as usual in a network by consulting routingtables.

If node B is, as assumed, an intermediate node the service manager innode B checks whether a circuit user slot may still be allocated in thecomplex frame to be generated on the outgoing leg of the medium link L2between node B and destination node C. If yes, the call packet ispropagated to node C, said call packet including the called number,information indicating that a circuit switched call is to be establishedand the slot number "yy" assigned to user X in the complex framegenerated from B toward C on link L2. The slot table in the transmittingmeans attached to the medium link L2 between B and C is updated and flagUCC in the subsequent frames transmitted on this link is set to0101"yy", where "yy" indicates the slot number assigned to user X onthis link.

Receiving means in node C attached to this link receives the sogenerated complex frames. The node C service manager determines thatdestination user Z is attached to this node and sent to node B a callconnected packet indicating that slot "zz" is assigned in the complexframe to be generated from node C toward node B, to user Z. The UCC flagis set to 0101"zz".

Detection in node B of the call connected packet and correct correlationwith the flag 0101"zz"" causes the call connected packet to bepropagated to node A, the slot table in the node B receiving meanscontrolling the medium link L2 between C and B is updated.

The call connected packet is propagated by node B to node A on the linkL1. Service manager in node B assignes slot"tt" to user Z and the UCCflag in the subsequent frames generated by node B transmitting meanscontrolling the link L1 between B and A is set to 0101"tt".

Detection in node A of the call connected packet and of flag 0101"tt"causes receiving slot table of the link L1 between node B and A to beupdated and completes the call initiation and call completion phases.

The switching tables in each node are updated when the call controlpackets: call request packet and call connected packet are propagatedthrough the node so as to contain the correlation between the slotnumber on the incoming link with the identification of the outgoing linkand slot number on this link. For example in node B, the switching slottables keep track of the correlation between xx on link L1 and yy onlink L2 and of zz on link L2 and tt on line L1.

The call control packets may have to be propagated through severalintermediate nodes depending upon the routing capabilities in thenetwork. The sames operations as described above are performed in eachnode.

If it were found in one of the intermediate node that a circuit userslot may not be allocated, this occurs when there is no more bandwidthavailable for circuit users, a clear request packet is sent by thisintermediate node to the originator node.

In case node B were not an intermediate node, but the destination node,the call connected packet or the clear packet as the case may be isdirectly sent by node B to node A with the flag 0101"tt" correlated tothe call connected packet.

When the called initiation phase and the call completion phases asdescribed above are completed, a new full duplex circuit referenced bythe slot numbers exists between nodes A and C. The bandwith used tocarry these slots has been removed from the asynchronous flow.

Consequently, the complex frames must at any time include some bitsdedicated to the asynchronous flow. It is the responsability of the nodeservice manager to determine the minimum bandwidth that must remainavailable for the asynchronous flow. In fact the call control packetsare sent using these bits in as many complex frames as required totransmit them. Whenever this minimum number is reached, attempt toestablish an additional circuit slot is rejected (clear phase)

The same mechanisms ars those described above in connection with thecall initiation and call completion phases are used for the clearinitiation and clear completion phases for deleting the circuit userslots, except that the C flag bit is set to 0 instead of being set to 1and the call request packet is replaced by a clear request packet andthe call connected packet is replaced by a clear confirmation packet.This causes the slots which were previously allocated during the callinitiation and call completion phases to be deleted.

In the above description, it has been assumed that the call controlpackets were sent on the same links as the frames in which slots have tobe added or deleted. However this is not a requirement. The call controlpackets may be sent on medium links through network nodes specifying onwhich links connected to the same nodes the circuit slots have to beadded or deleted. The flag are changed in the frames sent on theselinks. The service manager in each node waits for the two information:slot and link number in the control packets and new UCC flag, asdescribed in connection with FIG. 11.

The establishment of a circuit connection between two nodes may involvedup to four different links in the most general case instead of theunique link L1 as shown in FIG. 11:

first incoming link transporting the call request packet, in this casethe call control information comprises in addition to the slot numberthe called number, the calling number and the identification of a secondincoming link on which the circuit slot is to be established,

third outgoing link transporting the call connected packet in this casethe call control information comprises in addition to the slot number,the called number, the calling number and the identification of a fourthoutgoing link on which the circuit slot is to be established.

We claim:
 1. A method for configuring a succession of complex bit framesfor exchanging synchronous circuit switched bits such as digitized voicesignals which have been sampled at a frequency fs and coded with m bitsper sample and asynchronous packet switched bits, between nodesinterconnected by transmission links working at a plurality of bit ratesV said method comprising the steps of:generating in sequence a pluralityof complex frames each containing an integer number of bits Nc or Nc+1each of which complex frame includes n subframes where n is an integernumber equal to or greater than one, each of said complex frames beingprovided with a flag field f, the period of each said complex frame ismade to equal a value n.T+e where T is equal to the reciprocal of thesampling frequency fs used for providing the circuit switched bits, e isless than the link bit period, Nc is the integer part of V.n.T andselected to be as close as possible to an integer number Na which is thenumber of bits in the time period T on the link having the maximum bitrate Vmax and n is the integer part of Na/Nts where Nts is the integerpart of V.T; calculate the remaining bits R in each complex frame whereR=n[V.T-Nts], compare the calculated value of R to f if R is greaterthan f used the computed value of Nts in subsequent steps, if notdecrement Nts by one and recalculate R until R is greater than f and usethe decremented value of Nts in subsequent steps; allocate an integernumber of the Nts bits in each said subframe to an integer number ofcircuit switched bit slots and the remaining bits to asynchronous packetswitched bits; and partition the R remaining bits between the flag fieldf and residual bits r where r=R-f, said r residual bits being used forasynchronous packet switched bits, whereby the complex frames may beretrieved and distributed at the receiving end of the transmission linkby detecting the flag f and counting the bits in the complex frame.
 2. Amethod according to claim 1 characterized in that all of the subframescontain an equal number of bits.
 3. A method according to claim 1characterized in that at least one of the subframes includes at leastone additional bit of the r residual bits.
 4. A method according toclaim 1 characterized in that the f flag bits precede the subframes andthe r residual bits follow the subframes.
 5. A method according to anyone of claims 1 to 4 characterized in that the flag f includes at leasttwo bits which are set to different values.
 6. A method according toclaim 5 characterized in that the flag f includes more than two bits andthat preselected bits in excess of two are coded in selected complexframes for identifying a change in the status of a bit slot.